In view of large scale integration (LSI), four-time integration has been made at every two or three years, and is expected to be continued later. Plasma etching technology is an important base technology in forming fine patterns of a semiconductor, with a lithography technology. A basic mechanism of a plasma etching process includes adhesion of radicals generated by plasma generation to a film to be etched, and an ion assist etching reaction occurring due to ion implantation by an RF. So far, a parallel plate type, an electron cyclotron resonance (ECR) type, and an inductively coupled plasma (ICP) type have been used as a plasma source.
As a plasma etching method, a silicon nitride film on a silicon substrate or a silicon oxide film may be etched. In this case, it is necessary to increase selectivity of the silicon nitride film with respect to the silicon substrate or the silicon oxide film functioning as a base. Selectivity is a ratio between an etching rate of the silicon nitride film that is to be etched and an etching rate of a base film that is not etched, and the greater the selectivity is, the better.
The etching method in which the selectivity of the silicon nitride film with respect to the silicon substrate or the silicon oxide film is increased may be used in a method for producing, for example, a metal oxide semiconductor (MOS) transistor. An example of the method for producing the MOS transistor is as below.
FIGS. 24A through 24E show an example of a method for producing a MOS transistor. A large-scale LSI mostly uses a MOS transistor as a transistor. When forming a fine MOS transistor, a so-called “shallow junction” that forms a shallow p-n junction depth is necessary on a source and a drain of the MOS transistor. In order to realize the “shallow junction”, extension regions are formed on the source and the drain of the MOS transistor (for example, refer to Patent Reference 1).
First, as shown in FIG. 24A, a silicon oxide film 102 is formed on a silicon substrate 101. Next, a polysilicon film is deposited on the substrate, and then, the polysilicon is patterned by using a lithography technology and a dry etching process to form a gate electrode 103.
Next, in the process shown in FIG. 24B, a silicon oxide film 104 is deposited on the substrate by using a chemical vapor deposition (CVD) method. In addition, as shown in FIG. 24C, the silicon oxide film 104 is etched back to form offset spacers 104a on side surfaces of the gate electrode 103, and at the same time, a gate insulating layer 102a is formed under the gate electrode 103. In addition, ion implantation is performed by using the gate electrode 103 and the offset spacers 104a as a mask to form extension regions 108 on opposite side portions of the gate electrode 103 in the silicon substrate 101.
Next, in the process shown in FIG. 24D, an insulating layer such as a silicon oxide film is deposited on the substrate and etched back to form side wall spacers 109 formed of the silicon oxide film on outer portions of the offset spacers 104a. After that, ion implantation is performed by using the gate electrode 103, the offset spacers 104a, and the side wall spacers 109a as a mask to form high concentration source/drain regions 107 on outer portions of the extension regions 108 in the silicon substrate 101.
Then, in the process shown in FIG. 24E, after depositing a metal film such as a cobalt film or a nickel film on the substrate, and then, the silicon surface on which an upper portion of the gate electrode 103 and the high concentration source/drain regions 107 are exposed and the cobalt, the nickel, or the like react with each other to form, through self-alignment, a silicide film 110 for realizing low resistance on the surface on which the upper portion of the gate electrode 103 and the high concentration source/drain regions 107 are exposed.
When etching the fine gate electrode 103, plasma is generated in a processing container and an RF is applied to a holding stage on which the substrate is placed in the processing container, and then, ion is introduced on the substrate to perform a dry etching of the gate electrode 103.
In the process shown in FIG. 24D, when the side wall spacers 109 are formed on side walls of the gate electrode 103, a process of etching the silicon nitride film on the source/drain regions and the gate electrode 103 may be necessary. In this case, an etching operation with high selectivity of the silicon nitride film with respect to the silicon substrate or the silicon oxide film that is a base is necessary.
In addition, since the side wall spacers 109 are required to have an intensity that can bear the ion implantation, the silicon nitride film may be used as the side wall spacers 109. In addition, in the process shown in FIG. 24E, an etching for removing the side wall spacers 109 that are formed of the silicon nitride film used as a mask during the ion implantation is necessary. That is, an etching for selectively removing the side wall spacers 109 formed of the silicon nitride film with respect to the offset spacers 104a formed of the silicon oxide film is necessary.